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march 2014 altera corporation ds-1045 datasheet ? 2014 altera corporation. all rights rese rved. altera, arria, cyclone, enpiri on, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera cor poration and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademar ks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current spec ifications in accordance with altera's standard warranty, but reserves the right to make cha nges to any products and services at any time without notice. alt era assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein exce pt as expressly agreed to in writing by altera. altera customers are advised to obtain th e latest version of device specifications before relying on a ny published information and before placing or ders for products or services. 101 innovation drive san jose, ca 95134 www.altera.com subscribe iso 9001:2008 registered enpirion ? power datasheet EC7401QI 4-phase pwm controller with 8-bit dac code the altera? enpirion? EC7401QI controls microprocessor core voltage regulation by driving up to 4 synchronous-rectified buck channels in parallel . the EC7401QI can precision r ds (on) or dcr differential cu rrent sensing. multiphase buck converter architecture uses interleaved timing to multiply channel ripple frequency and re duce input and output ripple currents. lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area. microprocessor loads can genera te load transients with extremely fast edge rates. the EC7401QI features a high bandwidth control loop and ripple frequencies up to >4mhz to provide optimal response to the transients. today?s microprocessors requir e a tightly regulated output voltage position versus load current (droop). the EC7401QI senses current by utilizing pate nted techniques to measure the voltage across the on resistance, r ds (on), of the lower mosfets or dcr of the output inductor during the lower mosfet conduction intervals. cu rrent sensing provides the needed signals for precision droo p, channel-current balancing, and overcurrent protection. a programmable internal temperature compensation fu nction is implemented to effectively compensate for the temperature coefficient of the current sense element. a unity gain, differential amplif ier is provided for remote voltage sensing. any potential difference between remote and local grounds can be completely eliminated using the remote- sense amplifier. eliminating ground differences improves regulation and protection accur acy. the threshold-sensitive enable input is available to accura tely coordinate the start up of the EC7401QI with any other vo ltage rail. vid voltage scaling technology allows seamless on-the-fly vid changes. the offset pin allows accurate voltage offset settings that are independent of vid setting. features ? precision multiphase core voltage regulation - differential remote voltage sensing - ? 0.5% system accuracy over life, load, line and temperature - adjustable precision re ference-voltage offset ? precision r ds (on) or dcr current sensing - accurate load-line programming - accurate channel-current balancing - differential current sense ? microprocessor voltage identification input - vid voltage scaling technology - 8-bit vid input with selectable vr11 code and extended vr10 code at 6.25mv per bit - 0.5v to 1.6v operation range ? thermal sensing ? integrated programmable temperature compensation ? threshold-sensitive enable function for power sequencing and vtt enable ? overcurrent protection ? overvoltage protection ? 2-, 3- or 4-phase operation ? adjustable switching freque ncy up to 1mhz per phase ? package option - qfn compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline - qfn near chip scale package footprint; improves pcb efficiency, thinner in profile ? pb-free (rohs compliant) 09614 march 14, 2014 rev a
page 2 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation ordering information part number (note) part marking temp. (c) package (pb-free) pkg. dwg. # EC7401QI ec7401 -40 to +85 40 ld 6x6 qfn l40.6x6 *add ?-t? suffix for tape and reel. note: these altera enpirion pb-free plastic p ackaged products employ special pb-free ma terial sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termin ation finish, which is rohs compliant and compatible with both snpb and pb-free sol dering operations. altera enpirion pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb- free requirements of ipc/jedec j std-020. 09614 march 14, 2014 rev a
page 3 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation pin configuration EC7401QI (40 ld qfn) top view tsen pok fan hot fsw vid7 en_vtt en_pwr v diff vcc pwm3 isen3+ isen3- isen2- isen2+ pwm2 pwm4 isen4+ isen4- isen1- isen1+ tcomp vsen vgnd ss pwm1 idroop ref comp vfb 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 vid5 vid4 vid3 vid2 vid1 vrsel dac vid0 ofset vid6 gnd 09614 march 14, 2014 rev a
page 4 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation EC7401QI block diagram i_trip ? ? ? ? channel power-on reset (por) pwm1 pwm2 pwm3 pwm4 vcc vfb fsw clock and vid5 vid4 vid3 vid2 comp vsen generator sawtooth isen3- isen4+ vid1 vgnd vdiff pok ovp en_pwr 0.875v i_avg vid voltage scaling d/a ? current balance channel detect ofset three-state isen1+ isen2- channel current sense vid0 soft-start and fault logic offset ref +175mv x1 e/a oc pwm pwm pwm pwm en_vtt dac isen4- isen3+ isen2+ isen1- idroop 0.875v vid6 vid7 vrsel gnd tcomp gain tsen hot fan temperature compensation 1 n thermal monitoring compensation thermal ss 09614 march 14, 2014 rev a
page 5 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation typical application - 4-phase buck convert er with dcr sensing and external tcomp vfb EC7401QI comp ref idroop vdiff vsen vgnd en_vtt pok vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vrsel fan hot tsen tcomp ofset fsw ss en_pwr isen4- isen4+ pwm4 isen3- isen3+ pwm3 isen2- isen2+ pwm2 isen1- isen1+ pwm1 dac vcc 5v 12v ntc 5v vin vcc vcc_gd et4040qi pwm phase boot isen refin bgnd agnd pgnd sw 12v 3.3v 1.8v vin vcc vcc_gd et4040qi pwm phase boot isen refin bgnd agnd pgnd sw 12v 3.3v 1.8v vin vcc vcc_gd et4040qi pwm phase boot isen refin bgnd agnd pgnd sw 12v 3.3v 1.8v vin vcc vcc_gd et4040qi pwm phase boot isen refin bgnd agnd pgnd sw 12v 3.3v 1.8v load gnd 09614 march 14, 2014 rev a
page 6 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation absolute maximum ratings supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6v all pins . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to vcc + 0.3v esd ratings human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kv operating conditions supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature EC7401QI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal information thermal resistance (notes 1, 2) ? ja (c/w) ? jc (c/w) qfn package. . . . . . . . . . . . . . . . . 34 6.5 maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ? ja is measured in free air with the compon ent mounted on a high effective thermal conductivity test bo ard with ?direct attach? fe atures. see tech brief tb379 2. for ? jc , the ?case temp? location is the center of th e exposed metal pad on the package underside. electrical specifications operating conditions: vcc = 5v , unless otherwise specified parameter test conditions min typ max units vcc supply current vcc = 5vdc; en_pwr = 5vdc; r t = 100k ??? isen1 = isen2 = isen3 = isen4 = -70a -1520ma vcc = 5vdc; en_pwr = 0vdc; r t = 100k ? -1012ma por threshold vcc rising 4.3 4.5 4.7 v vcc falling 3.7 3.9 4.2 v en_pwr threshold nominal supply 0.850 0.875 0.910 v shutdown supply - 130 - mv power-on reset and enable en_vtt threshold rising 0.850 0.875 0.910 v hysteresis - 130 - mv falling 0.720 0.745 0.775 v reference voltage and dac system accuracy of EC7401QI (vid = 1v to 1.6v, t j = -40 c to +85 c ) (note 3) -0.6 - 0.6 %vid system accuracy of EC7401QI (vid = 0.5v to 1v, t j = -40 c to +85 c ) (note 3) -1 - 1 %vid vid pull-up -60 -40 -20 a vid input low level --0.4v vid input high level 0.8 - - v vrsel input low level --0.4v vrsel input high level 0.8 - - v dac source current -47ma dac sink current - - 300 a 09614 march 14, 2014 rev a
page 7 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation ref source current 45 50 55 a ref sink current 45 50 55 a pin-adjustable offset voltage at ofset pin of EC7401QI offset resistor connected to ground 388 400 412 mv voltage below vcc, offset resistor connected to vcc 1.552 1.600 1.648 v oscillators accuracy of switching frequency setting r t = 100k ?? 225 250 275 khz adjustment range of switching frequency (note 4) 0.08 - 1.0 mhz soft-start ramp rate r s = 100k ?? (notes 5, 6) - 1.563 - mv/s adjustment range of soft-start ramp rate (note 4) 0.625 - 6.25 mv/s pwm generator sawtooth amplitude -1.5- v max duty cycle -66.7- % error amplifier open-loop gain r l = 10k ? to ground (note 4) -96- db open-loop bandwidth c l = 100pf, r l = 10k ? to ground (note 4) -20-mhz slew rate c l = 100pf - 9 - v/s maximum output voltage 3.8 4.3 4.9 v output high voltage @ 2ma 3.6 - - v output low voltage @ 2ma --1.2v remote-sense amplifier bandwidth (note 4) -20-mhz output high current vsen - vgnd = 2.5v -500 - 500 a output high current vsen - vgnd = 0.6 -500 - 500 a pwm output pwm output voltage low threshold i load = 500a - - 0.5 v pwm output voltage high threshold i load = 500a 4.3 - - v sense current output (idroop and iout) sensed current tolerance isen1 = isen2 = isen3 = isen4 = 80a 76 80 84 a overcurrent trip level 90 100 110 a maximum voltage at idroop pin - 2 - v thermal monitoring and fan control tsen input voltage for fan trip 1.6 1.65 1.69 v tsen input voltage for fan reset 1.89 1.93 1.98 v tsen input voltage for hot trip 1.35 1.4 1.44 v tsen input voltage for hot reset 1.6 1.65 1.69 v leakage current of fan with externally pu ll-up resistor connected to vcc - - 30 a electrical specifications operating conditions: vcc = 5v , unless otherwise specified (continued) parameter test conditions min typ max units 09614 march 14, 2014 rev a
page 8 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation fan low voltage with 1.25k re sistor pull-up to vcc, i fan = 4ma - - 0.3 v leakage current of hot with externally pu ll-up resistor connected to vcc - - 30 a hot low voltage with 1.25k re sistor pull-up to vcc, i hot = 4ma - - 0.3 v vr ready and protection monitors leakage current of pok with externally pu ll-up resistor connected to vcc - - 30 a pok low voltage i pok = 4ma - - 0.3 v undervoltage threshol d vdiff falling 48 50 52 %vid pok reset voltage vdiff rising 58 60 62 %vid overvoltage protection threshold before valid vid 1.250 1.275 1.300 v after valid vid, the voltage above vid 150 175 200 mv overvoltage protection reset threshold 0.38 0.40 0.42 v notes: 3. these parts are designed and adjusted for accuracy with all errors in th e voltage loop included. 4. limits established by characterization and are not production tested. 5. during soft-start, vdac rises from 0 to 1.1v first an d then ramp to vid voltage after receiving valid vid. 6. soft-start ramp rate is determined by the adjustable soft-start oscillator frequ ency at the speed of 6.25mv per cycle. electrical specifications operating conditions: vcc = 5v , unless otherwise specified (continued) parameter test conditions min typ max units 09614 march 14, 2014 rev a
page 9 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation functional pin description vcc supplies the power necessary to operate the chip. the controller starts to operate wh en the voltage on this pin exceeds the ris ing por threshold and shuts down when the voltage on this pin drops below the falling por th reshold. connect this pin directly to a +5v supply. gnd bias and reference ground for the ic. th e bottom metal base of EC7401QI is the gnd. en_pwr this pin is a threshold-sensitive enable input for the controller. connecting the 12v supply to en_pwr through an appropriate resistor divider provides a means to sync hronize power-up of the controller and th e mosfet driver ics. when en_pwr is driven above 0.875v, the EC7401QI is active de pending on status of en_vtt, the intern al por, and pending fa ult states. driving en_pwr below 0.745v will clear all fa ult states and prime the EC7401QI to soft-start when re-enabled. en_vtt this pin is another threshold-se nsitive enable input for the controller. it?s t ypically connected to vt t output of vtt voltage regulator in the computer mother board. when en_vtt is dr iven above 0.875v, the EC7401QI is active depending on status of enll, the internal por, and pending fault states. driving en_vtt below 0.745v will clear all fault states and prime the EC7401QI to soft-start when re-enabled. fsw use this pin to set up the desired switchi ng frequency. a resistor, plac ed from fsw to ground will set the switching frequency. the relationship between the value of the resistor and the switc hing frequency will be described by an approximate equation. ss use this pin to set up the desired start-up oscillator frequency. a resi stor, placed from ss to ground will set up the soft-sta rt ramp rate. the relationship between the value of the resistor and the soft-start ra mp-up time will be desc ribed by an approximate equation. vid7, vid6, vid5, vid4, vi d3, vid2, vid1 and vid0 these are the inputs to the internal dac th at generates the reference voltage for out put regulation. connect these pins either to open-drain outputs with or without external pull-up resistors or to ac tive pull-up outputs. all vid pins have 40a internal pul l-up current sources that diminish to zero as the voltage rises above the logic-high leve l. these inputs can be pulled up externally as high as vcc plus 0.3v. when an off vid code causes shut -down, the controller needs to be reset before it starts again. vrsel use this pin to select internal vid code. when it is connected to gnd, the extended vr10 code is selected. when it?s floated or pulled to high, vr11 code is selected. this input can be pulled up as high as vcc plus 0.3v. vdiff, vsen, and vgnd vsen and vgnd form the precision differential remote-sense amplif ier. this amplifier converts the differential voltage of the remote output to a single-ended voltage re ferenced to local ground. vd iff is the amplifier?s output and the input to the regula tion and protection circuitry. connect vsen and vgnd to the sense pins of the remote load. vfb and comp inverting input and output of the error amplifier respectively. vf b can be connected to vdiff th rough a resistor. a properly ch osen resistor between vdiff and vfb can set the lo ad line (droop), when idroop pin is tied to vfb pin. the droop scale factor is set by the ratio of the isen resistors and the inductor dcr or the lower mosfet r ds (on). comp is tied back to vfb through an external rc network to compen sate the regulator. dac and ref the dac pin is the output of the precision internal dac reference. the ref pin is th e positive input of th e error amplifier. in typical applications, a 1k ? , 1% resistor is used between dac and ref to generate a precision offset voltage. this voltage is proportional to 09614 march 14, 2014 rev a
page 10 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation the offset current determined by the offset resistor from ofset to ground or vcc. a capacitor is used between ref and ground to smooth the voltage transition during vid voltage scaling operations. pwm1, pwm2, pwm3, pwm4 pulse width modulation outputs. connect these pins to the pwm input pins of the altera enpirion driver ic. the number of active channels is determined by the state of pwm3 and pwm4. tie pwm3 to vcc to configure for 2-phase operation. tie pwm4 to vcc to configure for 3-phase operation. isen1+, isen1-; isen2+, isen2-; is en3+, isen3-; isen4+ and isen4 the isen+ and isen- pins are current sense in puts to individual differential amplifiers . the sensed current is used for channel current balancing, overcurrent protection, and droop regulation. inactiv e channels should have their re spective current sense inputs le ft open (for example, open isen4+ and isen4- for 3-phase operation). for dcr sensing, connect each isen- pin to the node between the rc sense elements. tie the isen+ pin to the other end of the se nse capacitor through a resistor, r isen . the voltage across the sense capacito r is proportional to the inductor current. therefore, the sense current is proportional to the inductor current and scaled by the dcr of the inductor and r isen . when configured for r ds (on) current sensing, the isen1-, isen2-, isen 3-, and isen4- pins are grounded at the lower mosfet sources. the isen1+, isen2+, isen 3+, and isen4+ pins are then held at a virtual ground. therefore, a resistor, connected between these current sense pins and the drain terminals of the associat ed lower mosfet, will carry the current proportional to the current flowing through th at channel. the sensed current is determ ined by the negative voltage across the l ower mosfet when it is on, which is the channel current scaled by r ds (on) and r isen . pok pok indicates that the soft-start is comp leted and the output voltage is within th e regulated range around vid setting. it is a n open-drain logic output. when ocp or ovp occu rs, pok will be pulled to low. it will also be pulled low if the output voltage is below the undervoltage threshold. ofset the ofset pin provides a means to program a dc offset current for generating a dc offset voltage at th e ref input. the offset current is generated via an exte rnal resistor and precision inte rnal voltage references. the polar ity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofset pin should be le ft unterminated. tcomp temperature compensation scaling input. the vol tage sensed on the tsen pin is utilized as the temperat ure input to adjust ldroo p and the overcurrent protec tion limit to effectively compensate for the temperature coefficient of the current sense element. to implement the integrated temperature compen sation, a resistor divider ci rcuit is needed with one re sistor being connected from tcomp to vcc of the controller and anothe r resistor being connected from tcomp to gnd. changing the ratio of the resistor values will set the gain of the integrated thermal compensation. when integrated temperature co mpensation function is not used, connect tcomp to gnd. idroop idroop is the output pin of sensed average channel current whic h is proportional to load current . in the application which does not require loadline, leave this pin open. in the application which requires load line, connect this pin to vfb so that the sen sed average current will flow through the resi stor between vfb and vdiff to create a voltage drop which is proportional to load current. tsen tsen is an input pin for vr temperature measurement. connect this pin through ntc thermistor to gnd and a resistor to vcc of the controller. the voltage at this pin is reverse proportional to vr temperature. ec 7401qi monitors the vr temperature based o n the voltage at tsen pin an d outputs hot and fan signals. hot hot is used as an indication of high vr temperature. it is an open-drain logic output. it will be open when the measured vr temperature reaches a certain level. fan fan is an output pin with open-drain logic output. it will be open when the measured vr temperature reaches a certain level. 09614 march 14, 2014 rev a
page 11 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation operation multiphase power conversion microprocessor load current profiles have changed to the point that the advantages of multiphase power c onversion are impossibl e to ignore. the technical challe nges associated with producing a single-phase converter which is both cost-e ffective and thermal ly viable have forced a change to the cost -saving approach of multiphase. the EC7401QI controller helps reduce the complexity of implementation by integrating v ital functions and requiring mini mal output components. the bloc k diagram on page 4 provides top level views of multiphase power co nversion using the EC7401QI controller. interleaving the switching of each channel in a multipha se converter is timed to be symmetrically out of phase w ith each of the other channe ls. in a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycl e before the following channel. as a result, the 3-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. i n addition, the peak-to-peak ampl itude of the combined inductor currents is re duced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower rippl e amplitude mean that the de signer can use less per-channel inductance and lower total output capacitance for any performance specification. figure 1 illustrates the multiplicative effe ct on output ripple frequency. the three ch annel currents (il1, il 2, and il3) combi ne to form the ac ripple current and the dc load current. the ripple component has three times the ri pple frequency of each individua l channel current. each pwm pulse is terminated 1/3 of a cycle af ter the pwm pulse of the previous phase. the peak-to-peak curren t for each phase is about 7a, and the dc components of the inductor cu rrents combine to feed the load. to understand the reduction of ripple current amplitude in the multiphase circuit, examine equation 1 which represents an individual channel?s peak-t o-peak inductor current. figure 1. pwm and inductor-current waveforms for 3- phase converter 1s/div pwm2, 5v/div pwm3, 5v/div il2, 7a/div il3, 7a/div il1 + il2 + il3, 7a/div il1, 7a/div pwm1, 5v/div i p-p v in v out ? ?? 09614 march 14, 2014 rev a
page 12 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f sw is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multiphase convert ers, the capacitor current is the sum of the ripple currents from each of the individual cha nnels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase -shifted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output voltage ripple is a function of ca pacitance, ca pacitor equivalent series resistance (esr), and inductor ripple current . reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to redu ce input ripple current. input capacitance is determined in part by the maximum input ripple current. multiphase topologi es can improve overall system cost and size by lowering input ripple current and allowing th e designer to reduce the cost of input capacitance. the example in figure 2 illu strates input currents from a 3-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 deliver s 36a to a 1.5v load from a 12v input. the rms input capac itor current is 5.9a. compa re this to a single-phase converter also step ping down 12v to 1.5v at 36a. the single-phase converter has 11.9a rms input capacito r current. the single-phase converter must use an input capacitor bank w ith twice the rms current capacity as the equivalent 3-ph ase converter. figures 21, 22 and 23 in the section entitle d ?input capacitor selection? on page 41, ca n be used to determ ine the input-capacit or rms current based on load current, duty cycle, and the number of channels. they are provided as aids in determining the optimal input capacitor solution. figure 23 shows the single -phase input-capacitor rms current for comparison. pwm operation the timing of each channel is set by the number of active channels. the defa ult channel setting for the EC7401QI is four. the switching cycle is defined as th e time between pwm pulse termination signals of ea ch channel. the pulse termination signal is a n internally generated clock signal which triggers the falling edge of pwm signal. the cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the fsw pin and gr ound. each cycle begins when the clock signal commands the channe l pwm signal to go low. the pwm signals command the mosfet driver to turn on/off the channel mosfets. for 4-channel operation, the channel firing order is 4-3-2-1: pwm3 pulse terminates 1/4 of a cycle after pwm4, pwm2 output follows another 1/4 of a cycle after pwm3 , and pwm1 terminates another 1/4 of a cycle after pwm2. for 3-channel operation, the channel firing order is 3-2-1. connecting pwm4 to vcc selects three cha nnel operation and the pulse-termination times are spaced in 1/3 cycle increments. if pwm3 is connected to vcc, two channe l operation is selected and the pwm2 pul se terminates 1/2 of a cycle later. once a pwm signal transitions low, it is held low for a minimum of 1/3 cycle. this forced off time is required to ensure an accurate current sample. current sensing is described in the next section. after the fo rced off time expires, the pwm output is enabled. the pwm output state is driven by the position of the error amplifier output signal, v comp , minus the current correction figure 2. channel input currents and input-capacitor rms current for thr ee-phase converter input-capacitor current, 10a/div 1s/div channel 1 input current 10a/div channel 2 input current 10a/div channel 3 input current 10a/div i cp-p , v in nv out ? ?? 09614 march 14, 2014 rev a
page 13 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation signal relative to the sawtoot h ramp as illustrated in fi gure 7. when the modified v comp voltage crosses the sawtooth ramp, the pwm output transitions high. the mosfet dr iver detects the change in state of th e pwm signal and turns off the synchronous mosfet and turns on the upper mosfet. th e pwm signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the pwm signal low. current sampling during the forced off-time following a pwm transition low, the associated channel current sense amplifier uses the i sen inputs to reproduce a signal proportional to the inductor current (i l ). this current ge ts sampled starting 1/6 period after each pwm goes low and con tinuously gets sampled for 1/3 period, or until the pwm goes high, whichever comes first. no matter the current se nse method, the sense current (i sen ) is simply a scaled version of the inductor current. coincident with the falling edge of the pwm signa l, the sample and hold circuitry sa mples the sensed current signal (i sen ) as illustrated in figure 3. therefore, the sample current (i n ) is proportional to the output current and held for one switching cycle. the sample current is used for current balance, load-line regul ation, and overcur rent protection. current sensing the EC7401QI supports inducto r dcr sensing, mosfet r ds (on) sensing, or resistive sensing techniques. the inte rnal circuitry, shown in figures 4, 5, and 6, represents one channel of an n-channel c onverter. this circuitry is re peated for each channel in the converter, but may not be active depending on the status of the pwm3 and pwm4 pins, as desc ribed in ?pwm operation? on page 12. figure 3. sample and hold timing time pwm i l switching period i sen 0.5tsw sample current, i n 09614 march 14, 2014 rev a
page 14 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation inductor dcr sensing an inductor?s winding is characteristic of a distributed resistance as measured by the dcr (direct current re sistance) paramete r. consider the inductor dcr as a sepa rate lumped quantity, as shown in figure 4. the channel current (i l ) flowing through the inductor, will also pass through the dcr. equation 3 shows the s-domain equivalent vol tage across the inductor v l . a simple rc network across the inductor extrac ts the dcr voltage, as shown in figure 4. the voltage on the capacitor (v c ) can be shown to be proporti onal to the channel current (i l ) see equation 4. if the rc network components are selected such that the rc time constant (= r*c) matches the inductor time constant (= l/dcr), the voltage across the capacitor (v c ) is equal to the voltage drop across the dcr (i.e., proportional to the channel current). with the internal low-offset current amplifier, the capacitor voltage (v c ) is replicated across the sense resistor (r isen ). therefore the current out of isen+ pin (i sen ) is proportional to the inductor current. equation 5 shows that the ratio of the ch annel current to the sensed current (i sen ) is driven by the value of the sense resi stor and the dcr of the inductor. resistive sensing for accurate current se nse, a dedicated current-sense resistor (r sense ) in series with each output i nductor can serve as the current sense element (see figure 5). this technique is more accurate, but reduces overall converter effi ciency due to the additional p ower loss on the current sense element (r sense ). v l i l sl dcr + ? ?? ? = (eq. 3) v c s l dcr ------------- ? 1 + ?? ?? dcr i l ? ?? ? src 1 + ? ?? -------------------------------------------------------------------- - = (eq. 4) figure 4. dcr sensing configuration i n i sen i l dcr r isen ----------------- - = - + isen-(n) sample and hold EC7401QI internal circuit v in isen+(n) pwm(n) et4040qi r isen(n) dcr l inductor r v out c out (ptc) - + v c (s) c i l s ?? i sen i l dcr r isen ----------------- - ? = (eq. 5) 09614 march 14, 2014 rev a
page 15 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation equation 6 shows the ratio of the chan nel current to the sensed current (i sen ). mosfet r ds (on) sensing the controller can also sense the channel load curre nt by sampling the voltage across the lower mosfet r ds (on) (see figure 6). the amplifier is ground-reference by connecting the isen- pin to th e source of the lower mosfet. isen+ pin is connected to the phase node through the current sense resistor (r isen ). the voltage across r isen is equivalent to the voltage drop across the r ds (on) of the lower mosfet while it is conducting. the resulting current out of th e isen+ pin is proportional to the channel current i l . equation 7 shows the ratio of the chan nel current to the sensed current i sen . both inductor dcr and mosfet r ds (on) value will increase as the temperature increases. therefore the sensed current will increase as the temperature of the current sense element increase s. in order to compensate the temperature effect on the sensed current signal, a positive temperature coefficient (ptc) resistor can be selected for the sense resistor (r isen ), or the integrated temperature compensation function of EC7401QI should be util ized. the integrated temperat ure compensation function is described in ?temperature compensation? on page 33. i sen i l r sense r isen ----------------------- ? = (eq. 6) figure 5. sense resistor in series with inductors i n i sen i l r sense r isen -------------------------- = - + isen-(n) sample and hold EC7401QI internal circuit isen+(n) r isen(n) r sense l v out c out i l figure 6. mosfet r ds (on) current-s ensing circuit i n i sen i l r ds on ?? x r ? ?? i sen i l r ds on ?? r isen ------------------------ - = (eq. 7) 09614 march 14, 2014 rev a
page 16 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation channel-current balance the sensed current (i n ) from each active channel are summed together and di vided by the number of active channels. the resulting average current (i av g ) provides a measure of the total load current. channel current balance is achieved by comparing the sampled current of each channel to the average current to make an appr opriate adjustment to the wpm duty cycle of each channel. the current-balance method is illustrated in fi gure 7. in the figure, the average current combines with the channel 1 current (i 1 ) to create an error signal (i er ). the filtered error signal modifi es the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. channel current balance is essential in ac hieving the thermal advantage of multiphase operation. with good current balance, the power loss is equally dissipated over multiple devices and a greater area. voltage regulation the compensation network shown in figure 8 assures that the steady-state error in the output voltage is limited only to the err or in the reference voltage (output of the dac) an d offset errors in the ofset current sour ce, remote-sense and error amplifiers. alt era specifies the guaranteed tolerance of th e EC7401QI to include the combined tole rances of each of these elements. the output of the error amplifier (v comp ) is compared to the sawtooth waveform to generate the pwm si gnals. the pwm signals control the timing of the mosfet drivers and regulate the converter output to the spec ified reference voltage . the internal and external circuitry, which control voltage regulation, are illustrated in figure 8. figure 7. channel 1 pwm function and current-balance adjustment ?? n i avg i 4 * i 3 * i 2 ? + - + - f(j ? ) pwm1 i 1 v comp sawtooth signal i er note: *channels 3 and 4 are opti onal for 2 or 3 phase designs. filter 09614 march 14, 2014 rev a
page 17 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation the EC7401QI incorporates an internal differential remote-sen se amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the local c ontroller ground reference point resulting i n a more accurate means of sensing output voltage. connect the microprocessor se nse pins to the non-inverting input, v sen , and inverting input, vgnd, of th e remote-sense amplifier. the remote-sense output (v dif ), is connected to the inverting input of the error amplifier through an external resistor. a digital-to-analog convert er (dac) generates a reference volta ge based on the state of logic si gnals at pins vid7 through vid0 . the dac decodes the 8 6-bit logic signal (vid) into one of the di screte voltages shown in table 1. each vid input offers a 45a pull-up to an internal 2.5v source for us e with open-drain outputs. the pull-up current diminishes to zero above the logic thre shold to protect voltage-sensitive out put devices. external pull-up re sistors can augment the pull-up cu rrent sources if case leakage into the driving device is greater than 45a. figure 8. output voltage and load-line regulation with offset adjustment i avg external circuit EC7401QI internal circuit comp r c r fb vfb v diff vsen vgnd - + v droop error amplifier - + v out + differential remote-sense amplifier v comp c c ref dac r ref c ref - + v out - idroop 09614 march 14, 2014 rev a
page 18 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation table 1. vr10 vid table (with 6.25mv extension) vid4 400mv vid3 200mv vid2 100mv vid1 50mv vid0 25mv vid5 12.5mv vid6 6.25mv voltage (v) 010101 1 1.60000 010101 0 1.59375 010110 1 1.58750 010110 0 1.58125 010111 1 1.57500 010111 0 1.56875 011000 1 1.56250 011000 0 1.55625 011001 1 1.55000 011001 0 1.54375 011010 1 1.53750 011010 0 1.53125 011011 1 1.52500 011011 0 1.51875 011100 1 1.51250 011100 0 1.50625 011101 1 1.50000 011101 0 1.49375 011110 1 1.48750 011110 0 1.48125 011111 1 1.47500 011111 0 1.46875 100000 1 1.46250 100000 0 1.45625 100001 1 1.45000 100001 0 1.44375 100010 1 1.43750 100010 0 1.43125 100011 1 1.42500 100011 0 1.41875 100100 1 1.41250 100100 0 1.40625 100101 1 1.40000 100101 0 1.39375 100110 1 1.38750 100110 0 1.38125 100111 1 1.37500 100111 0 1.36875 09614 march 14, 2014 rev a
page 19 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation 101000 1 1.36250 101000 0 1.35625 101001 1 1.35000 101001 0 1.34375 101010 1 1.33750 101010 0 1.33125 101011 1 1.32500 101011 0 1.31875 101100 1 1.31250 101100 0 1.30625 101101 1 1.30000 101101 0 1.29375 101110 1 1.28750 101110 0 1.28125 101111 1 1.27500 101111 0 1.26875 110000 1 1.26250 110000 0 1.25625 110001 1 1.25000 110001 0 1.24375 110010 1 1.23750 110010 0 1.23125 110011 1 1.22500 110011 0 1.21875 110100 1 1.21250 110100 0 1.20625 110101 1 1.20000 110101 0 1.19375 110110 1 1.18750 110110 0 1.18125 110111 1 1.17500 110111 0 1.16875 111000 1 1.16250 111000 0 1.15625 111001 1 1.15000 111001 0 1.14375 111010 1 1.13750 111010 0 1.13125 table 1. vr10 vid table (with 6.25mv extension) (continued) vid4 400mv vid3 200mv vid2 100mv vid1 50mv vid0 25mv vid5 12.5mv vid6 6.25mv voltage (v) 09614 march 14, 2014 rev a
page 20 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation 111011 1 1.12500 111011 0 1.11875 111100 1 1.11250 111100 0 1.10625 111101 1 1.10000 111101 0 1.09375 111110 1off 111110 0off 111111 1off 111111 0off 000000 1 1.08750 000000 0 1.08125 000001 1 1.07500 000001 0 1.06875 000010 1 1.06250 000010 0 1.05625 000011 1 1.05000 000011 0 1.04375 000100 1 1.03750 000100 0 1.03125 000101 1 1.02500 000101 0 1.01875 000110 1 1.01250 000110 0 1.00625 000111 1 1.00000 000111 0 0.99375 001000 1 0.98750 001000 0 0.98125 001001 1 0.97500 001001 0 0.96875 001010 1 0.96250 001010 0 0.95625 001011 1 0.95000 001011 0 0.94375 001100 1 0.93750 001100 0 0.93125 001101 1 0.92500 001101 0 0.91875 table 1. vr10 vid table (with 6.25mv extension) (continued) vid4 400mv vid3 200mv vid2 100mv vid1 50mv vid0 25mv vid5 12.5mv vid6 6.25mv voltage (v) 09614 march 14, 2014 rev a
page 21 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation 001110 1 0.91250 001110 0 0.90625 001111 1 0.90000 001111 0 0.89375 010000 1 0.88750 010000 0 0.88125 010001 1 0.87500 010001 0 0.86875 010010 1 0.86250 010010 0 0.85625 010011 1 0.85000 010011 0 0.84375 010100 1 0.83750 010100 0 0.83125 table 2. vr11 vid 8 bit vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 00000000 off 00000001 off 000000101.60000 000000111.59375 000001001.58750 000001011.58125 000001101.57500 000001111.56875 000010001.56250 000010011.55625 000010101.55000 000010111.54375 000011001.53750 000011011.53125 000011101.52500 000011111.51875 000100001.51250 000100011.50625 000100101.50000 000100111.49375 000101001.48750 000101011.48125 table 1. vr10 vid table (with 6.25mv extension) (continued) vid4 400mv vid3 200mv vid2 100mv vid1 50mv vid0 25mv vid5 12.5mv vid6 6.25mv voltage (v) 09614 march 14, 2014 rev a
page 22 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation 000101101.47500 000101111.46875 000110001.46250 000110011.45625 000110101.45000 000110111.44375 000111001.43750 000111011.43125 000111101.42500 000111111.41875 001000001.41250 001000011.40625 001000101.40000 001000111.39375 001001001.38750 001001011.38125 001001101.37500 001001111.36875 001010001.36250 001010011.35625 001010101.35000 001010111.34375 001011001.33750 001011011.33125 001011101.32500 001011111.31875 001100001.31250 001100011.30625 001100101.30000 001100111.29375 001101001.28750 001101011.28125 001101101.27500 001101111.26875 001110001.26250 001110011.25625 001110101.25000 001110111.24375 001111001.23750 table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 09614 march 14, 2014 rev a
page 23 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation 001111011.23125 001111101.22500 001111111.21875 010000001.21250 010000011.20625 010000101.20000 010000111.19375 010001001.18750 010001011.18125 010001101.17500 010001111.16875 010010001.16250 010010011.15625 010010101.15000 010010111.14375 010011001.13750 010011011.13125 010011101.12500 010011111.11875 010100001.11250 010100011.10625 010100101.10000 010100111.09375 010101001.08750 010101011.08125 010101101.07500 010101111.06875 010110001.06250 010110011.05625 010110101.05000 010110111.04375 010111001.03750 010111011.03125 010111101.02500 010111111.01875 011000001.01250 011000011.00625 011000101.00000 011000110.99375 table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 09614 march 14, 2014 rev a
page 24 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation 011001000.98750 011001010.98125 011001100.97500 011001110.96875 011010000.96250 011010010.95625 011010100.95000 011010110.94375 011011000.93750 011011010.93125 011011100.92500 011011110.91875 011100000.91250 011100010.90625 011100100.90000 011100110.89375 011101000.88750 011101010.88125 011101100.87500 011101110.86875 011110000.86250 011110010.85625 011110100.85000 011110110.84375 011111000.83750 011111010.83125 011111100.82500 011111110.81875 100000000.81250 100000010.80625 100000100.80000 100000110.79375 100001000.78750 100001010.78125 100001100.77500 100001110.76875 100010000.76250 100010010.75625 100010100.75000 table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 09614 march 14, 2014 rev a
page 25 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation 100010110.74375 100011000.73750 100011010.73125 100011100.72500 100011110.71875 100100000.71250 100100010.70625 100100100.70000 100100110.69375 100101000.68750 100101010.68125 100101100.67500 100101110.66875 100110000.66250 100110010.65625 100110100.65000 100110110.64375 100111000.63750 100111010.63125 100111100.62500 100111110.61875 101000000.61250 101000010.60625 101000100.60000 101000110.59375 101001000.58750 101001010.58125 101001100.57500 101001110.56875 101010000.56250 101010010.55625 101010100.55000 101010110.54375 101011000.53750 101011010.53125 101011100.52500 101011110.51875 101100000.51250 101100010.50625 table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 09614 march 14, 2014 rev a
page 26 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation load-line regulation some microprocessor manufacturers require a precisely-controlled output resistance. this depende nce of output voltage on load current is often termed ?droop? or ?load line? regulation. by adding a well controll ed output impedance, the output voltage can effectively be level shifted in a direct ion which works to achieve the load-line regulation required by these manufacturers. in other cases, the designer ma y determine that a more cost-effective solution can be achieved by adding droop. droop can help to reduce the output-voltage spike that results from fast load-current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capacitors selected. by positioning the no-load voltage level near the upper specification limit, a larger negative spik e can be sustained wi thout crossing the lo wer limit. by adding a well controlled output impedance, the output voltage under load can effectively be le vel shifted down so that a larger positive spik e can be sustained without crossing the upper specification limit. as shown in figure 8, a current proportional to the average current of all active channels (i av g ) flows from vfb through a load- line regulation resistor r fb . the resulting voltage drop across r fb is proportional to the output cu rrent, effectively creating an output voltage droop with a steady-st ate value defined as equation 8: the regulated output voltage is reduced by the droop voltage (v droop ). the output voltage as a functi on of load current is derived by combining equation 8 with the appropriate sample curren t expression defined by the curre nt sense method employed. where v ref is the reference voltage, v ofset is the programmed offset voltage, i out is the total output current of the converter, r isen is the sense resistor connected to the isen+ pin, and r fb is the feedback resistor, n is the active channel number, and r x is the dcr, r ds (on), or r sense depending on the sensing method. therefore the equivalent loadli ne impedance, i.e. droop imped ance, is equal to equation 10: 101100100.50000 11111110 off 11111111 off table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage v droop i avg r fb = (eq. 8) v out v ref v ofset ? i out n ------------- r x r isen ----------------- -r fb ?? ?? ?? ? = (eq. 9) r ll r fb n ------------ r x r isen ----------------- - = (eq. 10) 09614 march 14, 2014 rev a
page 27 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation output-voltage offset programming the EC7401QI allows the designer to accurately adjust the offs et voltage. when a resistor (r ofset ) is connected between ofset to vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofset ) to flow into ofset. if r ofset is connected to ground, the voltage acro ss it is regulated to 0.4v, and i ofset flows out of ofset. a re sistor between dac and ref (r ref ) is selected so that the product (i ofset x r ofset ) is equal to the desired offset voltage . these functions are shown in figure 9. once the desired output offset voltage has been determined, us e equations 11 and 12 to set r ofset : for positive offset (connect r ofset to vcc): for negative offset (connect r ofset to gnd): vid voltage scaling modern microprocessors need to make changes to their core volta ge as part of normal operation. they direct the core-voltage regulator to do this by making changes to the vid inputs during regulator operation. the power manage ment solution is required to monitor the dac inputs and respond to on- the-fly vid changes in a controlled manne r. supervising the safe output voltage transition within the dac range of the proc essor without discontinuity or disruption is a necessary function of the core-voltag e regulator. the EC7401QI checks the vid inputs six times every switching cycle. if the vid code is found to have been changed, the controll er waits for half of a switching cycle before executing a 6.25mv step change. if the diff erence between dac le vel and the new vid code changes during the half-cycle wait ing period, no change to the dac output is made . if the vid code is more than 1 bit higher or lower than the dac (not recommended), the controller will execute 6. 26mv step change six times per cycle until vid and dac are equal. therefore it is important to ca refully control the rate of vi d stepping in 1-bit increments. in order to ensure the smooth transition of output voltage during vid change, a vid step change smoothing netw ork, composed of r ref and c ref , can be used. th e selection of r ref is based on the desired offset voltage as detailed in ?output- voltage offset programming? on page 27. the selection of c ref is based on the time duration for 1 bit vid change and the allowable delay time. r ofset 1.6 r ref ? v offset ----------------------------- - = (eq. 11) r ofset 0.4 r ref ? v offset ----------------------------- - = (eq. 12) vid voltage scaling d/a e/a v cc dac vfb ref ofset v cc gnd + - + - 0.4v 1.6v or gnd r ofset r ref EC7401QI figure 9. output voltage offset programming 09614 march 14, 2014 rev a
page 28 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation assuming the microprocessor controls the vid change at 1-bit every t vid , the relationship between the time constant of r ref and c ref network and t vid is given by equation 13. operation initialization prior to converter initialization, proper c onditions must exist on the enable inputs a nd vcc. when the conditions are met, the controller begins soft-start. once the output vol tage is within the proper window of operation, pok asserts logic high. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedan ce state to assure the drivers remain off. the following input conditions must be met before the EC7401QI is re leased from shutdown mode. 1. the bias voltage applied at vcc must reac h the internal power-on reset (por) rising threshold. once this threshold is reached , proper operation of all aspects of the ec7401q i is guaranteed. hysteresis between the rising and falling thre sholds assure that once enabled, the EC7401QI will not inadve rtently turn off unless the bias voltage drops substantiall y (see ?electrical specifications? on page 6). 2. the EC7401QI features an enable input (en_pwr) for power sequenc ing between the controller bias voltage and another voltage rail. the enable comparator holds the EC7401QI in sh utdown until the voltage at en _pwr rises above 0.875v. the enable comparator has about 130mv of hysteresis to prevent bounce. it is important that the dr iver ics reach their por level before the EC7401QI becomes enabled. th e schematic in figure 10 de monstrates sequencing the EC7401QI with the isl66xx family of mosfet drivers, which require 12v bias. 3. the voltage on en_vtt must be higher than 0.875v to enable th e controller. this pin is typica lly connected to the output of vtt vr. when all conditions above are sa tisfied, EC7401QI begins the soft -start and ramps the output vol tage to 1.1v first. after remaining at 1.1v for some ti me, EC7401QI reads the vid code at vid input pins. if the vid code is valid, EC7401QI will regulate the output to the final vid setting. if the vid code is off code, EC7401QI w ill shut down, and cy cling vcc, en_pwr or en_vtt is needed to restart. soft-start EC7401QI based vr has 4 periods during soft -start as shown in figure 11. afte r vcc, en_vtt and en_pwr reach their por/enable thresholds, the contro ller will have fixed delay peri od td1. after this delay period, the vr will begin first soft-s tart c ref r ref t vid = (eq. 13) figure 10. power sequencing using threshold-sensitive enable (en) function - + 0.875v external circuit EC7401QI internal circuit en_pwr +12v por circuit 10k ? ?? 09614 march 14, 2014 rev a
page 29 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation ramp until the output voltage reaches 1.1v v boot voltage. then, the controller will regulate the vr voltage at 1.1v for another fixed period td3. at the end of td3 period, EC7401QI reads the vid signals. if the vid code is valid, EC7401QI will initiate th e second soft-start ramp until the voltage r eaches the vid voltage minus offset voltage. the soft-start time is the sum of th e 4 periods as shown in equation 14. td1 is a fixed delay with the t ypical value as 1.36ms. td 3 is determined by the fixed 85s plus the time to obtain valid vid voltage. if the vid is valid before the out put reaches the 1.1v, the mi nimum time to validate the vid input is 500ns. therefore the minimum td3 is about 86s. during td2 and td4, EC7401QI digita lly controls the dac voltage change at 6.25 mv per step. the time for each step is determined by the frequency of the soft-start os cillator which is define d by the resistor r ss from ss pin to gnd. the second soft- start ramp time td2 and td4 can be ca lculated based on equations 15 and 16: for example, when vid is set to 1.5v and the rss is set at 100k ? , the first soft-start ramp ti me td2 will be 704s and the sec ond soft-start ramp time td4 will be 256s. after the dac voltage reaches the final vid setting, pok will be set to high with the fixed delay td5. the typical value for td 5 is 85s. fault monitoring and protection the EC7401QI actively monitors ou tput voltage and current to detect fault conditi ons. fault monitors tri gger protective measure s to prevent damage to a microprocessor load. one common power good indicator is pr ovided for linking to external system monitors. the schematic in figure 12 outlines the inte raction between the fault mo nitors and the pok signal. pok signal the pok pin is an open-drain logic output to indicate that the soft-start period is completed and the output voltage is within the regulated range. pok is pulled low during sh utdown and releases high afte r a successful soft-start and a fixed delay td5. pok will be pulled low when an unde rvoltage or overvoltage conditio n is detected, or th e controller is disabled by a reset from en_pwr, en_vtt, por, or vid off-code. undervoltage detection the undervoltage threshold is set at 50% of the vid code. when the output voltage at v sen is below the undervoltage threshold, pok is pulled low. t ss td1td2td3td4 +++ = (eq. 14) td2 1.1xr ss 6.25x25 ----------------------- - ? s ?? = (eq. 15) td4 v vid 1.1 ? ?? xr ss 6.25x25 ------------------------------------------------ ? s ?? = (eq. 16) figure 11. soft-start waveforms vout, 500mv/div en_vtt 500s/div td3 td4 td5 pok td1 td2 09614 march 14, 2014 rev a
page 30 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation overvoltage protection regardless of the vr being enabled or not, the EC7401QI overvolta ge protection (ovp) ci rcuit will be active after its por. the ovp thresholds are different under differen t operation conditions. when vr is not enab led and before the second soft-start, the ovp threshold is 1.275v. once the controll er detects valid vid input, the ovp trip point will be change d to vid plus 175mv. two actions are taken by the EC7401QI to protect the micr oprocessor load when an ove rvoltage condition occurs. at the inception of an overvoltage event, all pwm outputs are commanded low instan tly (less than 20ns) until the voltage at vdiff falls below 0.4v. this causes the drivers to turn on th e lower mosfets and pull the outpu t voltage below a level that might cause damage to the load . the pwm outputs remain low until vdiff falls be low 0.4v, and then pwm signals enter a high- impedance state. the drivers respond to the high-impedance input by turning off both upper and lower mosfets. if the overvoltage condition reoccurs, the ec7401q i will again command the lower mosfets to turn on. the EC7401QI will continue to protect the load in this fashion as long as the overvoltage condition occurs. once an overvoltage condition is detect ed, normal pwm operation ceas es until the EC7401QI is reset. cycling the voltage on en_pwr, en_vtt or vcc below the por-fa lling threshold will reset the controller. cycling the vid codes will not reset the controller. overcurrent protection EC7401QI has two levels of overcu rrent protection. each phase is protected from a sustained ove rcurrent condition on a delayed basis, while the combined phase currents are protected on an instantaneous basis. in instantaneous protection m ode, the EC7401QI utilizes th e sensed average current i av g to detect an overc urrent condition. see ?channel-current balance? on page 16 for more detail on how the aver age current is measured. the av erage current is continually compared with a constant 100 ? a reference current as shown in figure 12. once the average current exceeds the reference current, a comparator triggers th e converter to shutdown. figure 12. pok and protection circuitry - + vid + 0.175v v diff - + 100a i avg - + dac ov oc uv pok 50% soft-start, fault and control logic - + oc i 1 repeat for each channel 100a delay 09614 march 14, 2014 rev a
page 31 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation in individual overcurrent prot ection mode, the EC7401QI continuous ly compares the current of each channel with the same 100? a reference current. if any channel current exceeds the reference current continuou sly for eight consecutive cycles, the comparator triggers the converter to shutdown. at the beginning of overcurrent shutdown, the controller places all pwm signals in a high-impedance state within 20ns commanding the mosfet driver ics to turn off both upper and lower mosfets. the syst em remains in this state a period of 4096 switching cycles. if the controller is still enabled at the end of this wait period, it will attempt a soft-start. if the fault remains, the trip-retry cycles will continue indefinitely (as shown in fi gure 13) until either controller is disabled or the fault is cl eared. note that the energy delivered during trip-retry cycling is much less than during fu ll-load operation, so th ere is no thermal hazard during this kind of operation. 0a 0v 2ms/div output current figure 13. overcurrent behavior in hiccup mode. f sw = 500khz output voltage 09614 march 14, 2014 rev a
page 32 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation thermal monitoring (hot/fan) there are two thermal signals to indicate the temperature status of the voltage regulator: hot and fan. both fan and hot are open-drain outputs, and external pull-up resistors are required. fan signal indicates that the temperature of the voltage regulator is high and more cooling airflow is needed. hot signal can b e used to inform the system th at the temperature of the volta ge regulator is too high and the cpu should reduce its power consumption. hot signal may be tied to the cpu?s proc_hot signal. the diagram of thermal monitoring function bl ock is shown in figure 14. one ntc resist or should be placed close to the power stage of the voltage regulator to sense th e operational temperature, and one pull-up resistor is needed to form the voltage div ider for tsen pin. as the temperature of the power stage increases, the resistance of the ntc will reduce, resulting in the reduced voltage at tsen pin. figure 15 shows th e tsen voltage over the temperature for a typical design with a recommended 6.8k ? ntc (p/n: nths0805n02n6801 from vishay) and 1k ? resistor r tsen1 . we recommend using those resistors for the accurate temperature compensation. there are two comparators with hysteresis to compare the tsen pin voltage to the fixed thres holds for fan and hot signals respectively. fan signal is set to high when tsen voltage is lower than 33% of vcc voltage, a nd is pulled to gnd when tsen voltage increases to above 39% of vcc vo ltage. fan is set to high when tsen volta ge goes below 28% of vcc voltage, and is pulled to gnd when tsen voltage goes back to above 33% of vcc voltage. figure 16 shows the operation of those signals. figure 14. block diagram of thermal monitoring function 0.28v cc 0.33v cc o c r tsen1 r ntc v cc tsen fan hot figure 15. the ratio of tsen voltage to ntc temperature with recommended parts v tsen /v cc vs temperature 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 temperature (c) v tsen /v cc (%) 09614 march 14, 2014 rev a
page 33 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation based on the ntc temperature characte ristics and the desired threshold of hot signal, the pull-up resistor r tsen1 of tsen pin is given by: r ntc(t3) is the ntc resistance at the hot threshold temperature t3. the ntc resistance at the set point t2 and releas e point t1 of fan signal can be calculated as: with the ntc resistance value obtained fro m equations 18 and 19, the temperature valu e t2 and t1 can be found from the ntc datasheet. temperature compensation EC7401QI supports inductor d cr sensing, mosfet r ds (on) sensing, or resistive sensi ng techniques. both inductor dcr and mosfet r ds (on) have the positive temperature coef ficient, which is about +0.38%/c. because the voltage across inductor or mosfet is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor dcr or mosfet r ds (on). in order to obtain the correct current information, there should be a way to correct the temperat ure impact on the current sens e component. EC7401QI provides two methods: integrated temper ature compensation and external temperature compensation. integrated temperature compensation when tcomp voltage is equal or greate r than vcc/15, EC7401QI will utilize th e voltage at tsen and tcomp pins to compensate the temperature impact on the sensed current. the block diagram of this f unction is shown in figure 17. figure 16. hot and fan signal vs tsen voltage temperature (c) tsen fan hot 0.39*v cc 0.33*v cc 0.28*v cc t1 t2 t3 r tsen1 2.75xr ntc t3 ?? = (eq. 17) r ntc t2 ?? 1.267xr ntc t3 ?? = (eq. 18) r ntc t1 ?? 1.644xr ntc t3 ?? = (eq. 19) 09614 march 14, 2014 rev a
page 34 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation when the tsen ntc is placed close to the current sense component (inductor or mosfet), the te mperature of the ntc will track the temperature of the current sense component. therefore the tsen voltage can be utilized to obtain the temperature of t he current sense component. based on vcc voltage, EC7401QI converts the ts en pin voltage to a 6-bit tsen digita l signal for temperature compensation. with the non-linear a/d converter of ec74 01qi, tsen digital signal is linearly proportional to the ntc temperature. for accurate temperature compensation, the rati o of the tsen voltage to the ntc temperat ure of the practical design should be simil ar to that in figure 15. depending on the location of the ntc and the airflow, the ntc may be cooler or hotter than the current sense component. tcomp pin voltage can be utilized to corre ct the temperature difference between nt c and the current sense component. when a different ntc type or different vo ltage divider is used for the tsen function, tcom p voltage can also be used to compensate for the difference between the recommended tsen voltage curve in figure 16 and that of the actual design. according to the vcc voltage, EC7401QI converts the tcomp pin voltage to a 4-bi t tcomp digital signal as tcomp factor n. tcomp factor n is an integer between 0 a nd 15. the integrated temperature compensati on function is disabled for n = 0. for n = 4, the ntc temperature is equal to the temperature of the curre nt sense component. for n < 4, the ntc is hotter than the current sense component. the ntc is cooler than the current sense com ponent for n > 4. when n > 4, the larger tcomp factor n, the larger the difference between the ntc temperature and the temperature of the current sense component. EC7401QI multiplexes the tcomp factor n w ith the tsen digital signal to obtain th e adjustment gain to compensate the temperature impact on the sensed channel current. the compensated channel curr ent signal is used for droop and overcurrent protection functions. design procedure 1. properly choose the voltage divider for tsen pin to match the tsen voltage v s temperature curve with the recommended curve in figure 15. 2. run the actual board under the full load and the desired cooling condition. 3. after the board reaches the thermal steady state, record the temperature (t csc ) of the current sense component (inductor or mosfet) and the voltage at tsen and vcc pins. 4. use equation 20 to calculat e the resistance of the ts en ntc, and find out the corresponding ntc temperature t ntc from the ntc datasheet. figure 17. block diagram of integrated temperature compensation o c r tm1 r ntc tm r tc1 r tc2 tcomp v cc non-linear a/d 4-bit a/d droop & over current protection i 1 i 2 i 3 i 4 k i d/a channel current sense i sen4 i sen3 i sen2 i sen1 v cc channel current sense non-linear a/d 4-bit a/d droop and overcurrent protection tsen r tsen1 r ntc t ntc ?? ? tsen --------------------------------------------- - = (eq. 20) 09614 march 14, 2014 rev a
page 35 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation 5. use equation 21 to calculate the tcomp factor n: 6. choose an integral number close to the above result for the tcomp factor. if this factor is higher than 15, use n = 15. if it i s less than 1, use n = 1. 7. choose the pull-up resistor r tc1 (typical 10k ? ). 8. if n = 15, do not need the pull-down resistor r tc2 , otherwise obtain r tc2 by equation 22: 9. run the actual board under full lo ad again with the proper resist ors connected to the tcomp pin. 10. record the output voltage as v1 immediately after the output vol tage is stable with the full load. record the output voltage as v2 after the vr reaches the thermal steady state. 11. if the output voltage increases over 2m v as the temperature increases, i.e. v2 - v1 > 2mv, reduce n and redesign r tc2 ; if the output voltage decreases over 2mv as th e temperature increases, i.e. v1 - v2 > 2mv, increase n and redesign r tc2 . the design spreadsheet is available for those calculations. external temperature compensation by setting the voltage of tcomp pin to 0, the integrated te mperature compensation function is disabled. and one external temperature compensation network, shown in figure 18, can be used to cancel the temp erature impact on the droop (i.e. load line ). the sensed current will flow out of idroop pin and de velop the droop voltage across the resistor equivalent (r fb ) between vfb and vdiff pins. if r fb resistance reduces as the temperature increases, the temperature impact on th e droop can be compensated. an ntc resistor can be placed close to the power stage and used to form r fb . due to the non-linear temperature characteristics of the ntc, a resistor networ k is needed to make the equivale nt resistance between vfb and vdiff pin is reverse proportional to th e temperature. the external temperature compensation netw ork can only compensate the temperature impact on the droop, while it has no impact to the sensed current inside EC7401QI. th erefore this network cannot co mpensate for the temperatur e impact on the overcurrent protection function. current sense output the current from idroop pin is the sensed average current inside EC7401QI. in typical application, idroop pin is connected to vfb pin for the application where load line is required. when load line function is not needed, idroop pin can used to obtain t he load current information: with one resistor from idroop pin to gnd, the voltage at idroop pin will be proportional to the load current. the resistor from idroop to gnd shoul d be chosen to ensure that the voltage at idroop pin is le ss than 2v under the maximum load current. n 209x t csc t ? ntc ?? 3xt ntc 400 + ------------------------------------------------------- - 4 + = (eq. 21) r tc2 nxr tc1 15 n ? ----------------------- = (eq. 22) figure 18. voltage at idroop pin with a resistor placed from idroop pin to gnd when load current changes fb o c vdiff comp idroop v fb o c v diff comp idroop 09614 march 14, 2014 rev a
page 36 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation general design guide this design guide is intended to provide a high-level explanation of the steps nece ssary to create a multiphase power converter . it is assumed that the reader is familiar with many of the basic skills an d techniques referenced below. power stages the first step in designing a multiphase c onverter is to determine the number of phase s. this determination depends heavily on the cost analysis which in turn depends on sy stem constraints that differ from one design to the next. principally, the designer wi ll be concerned with whether components can be mounted on both sides of the circuit board; whether through- hole components are permitted; and the total board space available for power-supply circuitry. ge nerally speaking, the most economical solutions ar e those in which each phase handles between 15a and 20a. all surface-mount designs w ill tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a pe r phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to conduct; the switching frequency; the capability of the mosfets to dissip ate heat; and the availability and na ture of heat si nking and air flow. lower mosfet power calculation the calculation for heat dissipated in the lo wer mosfet is simple, since virtually all of th e heat loss in the lower mosfet is due to current conducted through the channel resistance (r ds (on)). in equation 23, i m is the maximum continuous output current; i pp is the peak-to-peak inductor current (s ee equation 1); d is the duty cycle (v out /v in ); and l is the per- channel inductance. an additional term can be added to the lo wer-mosfet loss equation to account for a dditional loss accrued dur ing the dead time when inductor current is flowing through the lower-mosfet body di ode. this term is dependent on the diode forward voltage at i m , v d(on) ; the switching frequency, f sw ; and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower- mosfet conduction inte rval respectively. thus the total maximum power dissipated in each lower mosfet is approxima ted by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds (on) losses, a large portion of the uppe r-mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a s ubstantially higher portion of th e upper-mosfet losses are depe ndent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper- mosfet switching times; the lower-mosfe t body-diode reverse-recovery charge (q rr ) and the upper mosfet r ds (on) conduction loss. when the upper mosfet turns off, the lower mosfet does not conduc t any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the curre nt in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 25, the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduc t and this transition occurs over a time t 2 . in equation 26, the approximate power loss is p up,2 . p low 1 ? r ds on ?? i m n ----- - ?? ?? ?? 2 1d ? ?? i lp-p , 2 1d ? ?? 12 ---------------------------------- + = (eq. 23) p low 2 ? v don ?? f sw i m n ----- - i p-p 2 ---------- -+ ?? ?? t d1 i m n ----- - i p-p 2 ---------- - ? ?? ?? ?? t d2 + = (eq. 24) p up 1 , v in i m n ----- - i p-p 2 ---------- -+ ?? ?? t 1 2 ---- ?? ?? ?? f sw ? (eq. 25) p up 2 , v in i m n ----- - i p-p 2 ---------- - ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f sw ? (eq. 26) 09614 march 14, 2014 rev a
page 37 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation a third component involves the lower mosfet?s reverse-recovery charge (q rr ). since the inductor curr ent has fully commutated to the upper mosfet before the lower-mosfet?s body diode can draw all of q rr , it is conducted through the upper mosfet across v in . the power dissipated as a result is p up,3 and is approximately finally, the resist ive part of the upper mosfet?s is given in equation 28 as p up,4 . the total power dissipated by the upper mosfet at full load ca n now be approximated as the su mmation of the results from equations 25, 26, and 27. since the power equations depend on mosfet parameters, choosing the co rrect mosfets can be an iterative process involving repetitive soluti ons to the loss equations for differen t mosfets and different switching frequencie s. current sensing resistor the resistors connected be tween these pins and the respective phase nodes determine the ga ins in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. select valu es for these resistors based on the room temperature r ds (on) of the lower mosfets, dcr of inductor or a dditional resistor; the full -load operating current, i fl ; and the number of phases, n using equation 29. in certain circumstances, it may be necessary to adjust the value of one or more isen resistor. when the components of one or more channels are inhibited from effectivel y dissipating their heat so th at the affected channels ru n hotter than desired, choo se new, smaller values of r isen for the affected phases (see the section entitled ?channel-current balance? on page 16). choose r isen2 in proportion to the desired decrease in temperature rise in order to cause proportionally less curre nt to flow in the hotter phase. in equation 30, make sure that ? t 2 is the desired temperature rise above the ambient temperature, and ? t 1 is the measured temperature rise above the ambien t temperature. while a single adjustment according to equation 30 is usually sufficient, it ma y occasionally be necessary to adjust r isen two or more times to achieve optimal thermal balance between all channels. load-line regulation resistor the load-line regulation resistor is labelled r fb in figure 8. its value depends on th e desired full load droop voltage (v droop in figure 8). if equation 29 is used to select each isen resistor, the load-line re gulation resistor is as shown in equation 31. if one or more of the isen resistors is ad justed for thermal balance, as in equati on 30, the load-line regulation resistor shou ld be selected according to equation 32 where i fl is the full-load operating current and r isen(n) is the isen resistor connected to the n th isen pin. compensation the two opposing goals of compensating the voltage regulator are stab ility and speed. depending on whether the regulator employs the optional load-line re gulation as described in load-l ine regulation, there are two distinct methods for achieving th ese goals. compensating load-line regulated converter the load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter lc resonant frequenc y split with the introduction of current informat ion into the control loop. the final locatio n of p up 3 , v in q rr f sw = (eq. 27) p up 4 , r ds on ?? i m n ----- - ?? ?? ?? 2 d i p-p 2 12 ---------- - d+ ? r isen r x 70 10 6 ? ? ----------------------- i fl n ------- - = (eq. 29) r isen 2 , r isen ? t 2 ? t 1 ---------- = (eq. 30) r fb v droop 70 10 6 ? ? ------------------------ - = (eq. 31) r fb v droop i fl r ds on ?? -------------------------------- r isen n ?? n ? = (eq. 32) 09614 march 14, 2014 rev a
page 38 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation these poles is determined by the system function, the gain of the current sign al, and the value of th e compensation components, r c and c c . since the system poles and zero are affect ed by the values of the components that ar e meant to compensate them, the solution to the system equation becomes fairly complica ted. fortunately there is a simple approxi mation that comes very close to an optimal solution. treating the system as though it we re a voltage-mode regulator by compensati ng the lc poles and the esr zero of the voltage-mode approximation yields a solution that is alwa ys stable with very close to ideal transient performance. the feedback resistor, r fb , has already been chosen as outli ned in ?load-line regulation resi stor? on page 37. se lect a target bandwidth for the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channe l switching frequency. the values of the compensation components depend on the relationships of f 0 to the lc pole frequency and the esr zero frequency. for each of the three cases which follow, there is a separate set of equations for the compensation components. in equation 33, l is the per-cha nnel filter inductance divided by the number of active channels; c is the sum total of all outp ut capacitors; esr is the e quivalent-series resistance of the bulk output-filt er capacitance; and v pp is the peak-to-peak sawtooth signal amplitude as describe d in figure 7 and ?electrica l specifications? on page 6. figure 19. compensation configuration for load-line regulated EC7401QI circuit EC7401QI comp c c r c r fb idroop vdiff - + v droop c 2 (optional) vfb 1 2 ? ? ? case 1: 1 2 ? ? ?? ? ? ?? ? ?? case 2: (eq. 33) f 0 1 2 ? ?? ? ?? ?? ? case 3: 09614 march 14, 2014 rev a
page 39 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 20). keep a position available for c 2 , and be prepared to install a high-frequency capacitor of between 22pf and 150pf in ca se any leading-edge jitter problem is noted. once selected, the compensation values in equation 33 assure a stable converter with reasonable transient performance. in most cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an os cilloscope until no fu rther improvement is noted. normally, c c will not need adjustment. keep the value of c c from equation 33 unless some performance issue is noted. compensation without load-line regulation the non load-line regulated converter is accurately modeled as a voltage-mode regula tor with two poles at the lc resonant frequency and a zero at the esr frequency. a type iii controller, as shown in figure 20, provides the necessary compensation. the first step is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient performance but not high er than 1/3 of the switching frequency. the type-iii compensator has an extra high- frequency pole, f hf . this pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high- order pole and zero frequencies. a good general rule is to choose f hf = 10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much ph ase shift below the system bandwidth. in the solutions to the compensation equati ons, there is a single degree of freedom. for the solutions presented in equation 34 , r fb is selected arbitrarily. the rema ining compensation components are then selected accord ing to equation 34. in equation 34, l is the per-cha nnel filter inductance divided by the number of active channels; c is the sum total of all outp ut capacitors; esr is the e quivalent-series resistance of the bulk output-filt er capacitance; and v p-p is the peak-to-peak sawtooth signal amplitude as describe d in figure 7 and ?electrica l specifications? on page 6. figure 20. compensation circuit for EC7401QI based converter without load-line regulation EC7401QI comp c c r c r fb vfb idroop vdiff c 2 c 1 r 1 c c 0.75v in 2 ? ? ?? ?? ? ?? ? ?? ?? ? ? ?? ?? ?? ?? ? ---------------------------------------- - = c 1 lc c esr ?? ? r fb ---------------------------------------- - = c 2 0.75v in 2 ? ?? 09614 march 14, 2014 rev a
page 40 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation output filter design the output inductors and the output capacito r bank together to form a low-pass filt er responsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient en ergy until the regulator can respond. because i t has a low bandwidth compared to the switching frequency, the output filt er necessarily limits the system transient response. the outp ut capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the out put capacitor bank is usually the most costly (a nd often the largest) part of the circuit. out put filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacit ors are the maximum size of the load step, ? i; the load-current slew rate, di/dt; and th e maximum allowable out put-voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance (esr) and esl (equivalent series inductance). at the beginning of the load transient, th e output capacitors supply all of the tran sient current. the output voltage will init ially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, th e voltage drop across th e esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl a nd esr so that the total output-voltage deviat ion is less than the allowable maximum. neglecting the contribution of inductor curr ent and regulator response, th e output voltage initiall y deviates by an amount: the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bul k capacitors having high capa citance but limited high-frequency performance. mini mizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increase s. minimizing the esr of the bul k capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of th e output-voltage ripple. as the bulk capacitors sink and source t he inductor ac ripple current (see ?interleav ing? on page 11 and equation 2), a voltage de velops across the bul k-capacitor esr equal to i c,p-p (esr). thus, once the output ca pacitors are selected, the maxi mum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance. . since the capacitors are supplyi ng a decreasing portion of the load current while the regulator recovers from the transient, th e capacitor voltage becomes slightly depleted. the out put inductors must be capable of assu ming the entire load current before th e output voltage decreases more than ? v max . this places an uppe r limit on inductance. equation 37 gives the upper limit on l for the cases when the trailing edge of the curre nt transient causes a greater output-vo ltage deviation than the leading edge. equation 38 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50 %. nevertheless, both inequalities should be evaluate d, and l should be selected ba sed on the lower of the two results. in each equation, l is the per-channe l inductance, c is the total output capacita nce, and n is the number of active channels. switching frequency there are a number of variables to consider when choosing the switchi ng frequency, as there are considerable effects on the upp er- mosfet loss calculation. these effects are outlined in ?mo sfets? on page 36, and they esta blish the upper limit for the switching frequency. the lower limit is esta blished by the requirement fo r fast transient response and small output -voltage rip ple as outlined in ?output filter design? on pa ge 40. choose the lowest swit ching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determin ed by the selection of the frequency-setting resistor, r t (see the figure labelled typical application on page 5). equation 39 is provided to assist in selecting the correct value for r t . ? v esl ?? di dt ---- -esr ??? i + ? l esr ?? v in nv out ? ?? ?? v out f sw v in v pp max ?? ----------------------------------------------------------- - ? l 2ncv o ? i ?? 2 --------------------- ? v max ? i esr ?? ? ? l 1.25 ?? nc ? i ?? 2 ------------------------- - ? v max ? i esr ?? ? v in v o ? ?? ?? ? r t 2.5x10 10 f sw ------------------------- - = 09614 march 14, 2014 rev a
page 41 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capacity must be sufficient to handle the ac component of th e current drawn by the upper mosfets which is related to duty cycle and th e number of active phases. . 0.3 0.1 0 0.2 input-capacitor current (i rms /i o ) figure 21. normalized input-capacitor rms current vs duty cycle for 2-phase converter 00 . 4 1 . 0 0.2 0.6 0.8 duty cycle (v o /v in ) i l,p-p = 0 i l,p-p = 0.5 i o i l,p-p = 0.75 i o duty cycle (v o/ v in ) figure 22. normalized input- capacitor rms current vs duty cycle for 3-phase converter 00 . 4 1 . 0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l,p-p = 0 i l,p-p = 0.25 i o i l,p-p = 0.5 i o i l,p-p = 0.75 i o 09614 march 14, 2014 rev a
page 42 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation for a two phase design, use figure 21 to de termine the input-capacitor rms current re quirement given the duty cycle, maximum sustained output current (i o ), and the ratio of the per-phase peak-to-peak inductor current (i l,p-p ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors requi red to support the rms current calculated . the voltage rating of the capa citors should also be at least 1.25 times greater than the maximum input voltage. figures 22 and 23 provide the same input rms current information for three and four phase designs respecti vely. use the same approach to selecting th e bulk capacitor type and number as described above. low capacitance, high-fre quency ceramic capacitors are needed in addition to the bulk capacito rs to suppress le ading and fallin g edge voltage spikes. the result from the hi gh current slew rates produced by the upper mosfets turn on and off. select low esl ceramic capacitors and pl ace one as close as possible to each upper mosfet drain to minimize board parasitic impedances and maximize suppression. multiphase rm s improvement figure 23 is provided as a refe rence to demonstrate the dram atic reductions in input-cap acitor rms current upon the implementation of the multiphase topology. for example, compare the input rms current requirements of a two-phase converter versus that of a single phase. assume both converters have a duty cycle of 0.25, maximum sustained output current of 40a, and a ratio of i l,p-p to i o of 0.5. the single phase converter would require 17.3a rms current capacity while the two-phase converter would only require 10.9a rms . the advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single phase approach. layout considerations the following layout strategies are intend ed to minimize the impact of board parasitic impedances on conver ter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. these sections highlight some important practices whic h should not be overlooked during the layout process. component placement within the allotted implementation area, or ient the switching components first. the switching compone nts are the most critical because they carry large amounts of energy and tend to generate high levels of noise. switching component placement should take into account power dissipation. align the output inductors and mosfets such th at space between the co mponents is minimized while creating the phase plane. place the mosfet driver ic as close as possible to the mosfets they control to reduce the parasitic impedances due to trace length betwee n critical driver input and output signa ls. if possible, dupl icate the same plac ement of these components for each phase. next, place the input and output capacito rs. position one high-frequency ceramic input capacitor next to each upper mosfet drain. place the bulk input capacitors as close to the upper mosfet drains as dictated by the component size and dimensions. long distances between input capacitors and mosfet drains result in too much trace induc tance and a reduction in capacitor performance. locate the output capacitors be tween the inductors and the load, while ke eping them in close proximity to the microprocessor socket. figure 23. normalized input-capacitor rms current vs duty cycle for single-phase converter 00 . 4 1 . 0 0.2 0.6 0.8 duty cycle (v o/ v in ) input-capacitor current (i rms/ i o ) 0.6 0.2 0 0.4 i l,p-p = 0 i l,p-p = 0.5 i o i l,p-p = 0.75 i o 09614 march 14, 2014 rev a
page 43 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation the EC7401QI can be placed off to one side or centered relative to the indivi dual phase switching compone nts. routing of sense lines and pwm signals will guide final placement. critical small signal components to place close to the controller include the isen resistors, r t resistor, feedback resistor , and compensation components. bypass capacitors for the EC7401QI and isl66xx driver bias supplies must be placed next to their respective pins. trace parasit ic impedances will reduce their effectiveness. plane allocation and routing dedicate one solid layer, usua lly a middle layer, for a ground plane. make all critical component ground connections with vias to this plane. dedicate one additional layer for power planes; breaking the plane up into smalle r islands of common voltage. use t he remaining layers for signal wiring. route phase planes of copper filled polygons on the top and bottom once th e switching component placement is set. size the trac e width between the driver gate pins and th e mosfet gates to carry 4a of current. when routing components in the switching path, use short wide traces to reduce th e associated para sitic impedances. document revision history the table lists the revision history for this document. date version changes march 2014 1.0 initial release. 09614 march 14, 2014 rev a
page 44 EC7401QI 4-phase pwm controller with 8-bit dac code march 2014 altera corporation package outline drawing l40.6x6 40 lead quad flat no-lead plastic package rev 3, 10/06 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is meas ured di mensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.15 index area pin 1 a 6.00 b 6.00 31 36x 0.50 4.5 4x 40 pin #1 index area bottom view 40x 0 . 4 0 . 1 20 b 0.10 11 ma c 4 21 4 . 10 0 . 15 0 . 90 0 . 1 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. detail "x" 0 . 05 max. 0 . 2 ref c 5 side view 1 10 30 typical recommended land pattern ( 5 . 8 typ ) ( 4 . 10 ) ( 36x 0 . 5 ) ( 40x 0 . 23 ) ( 40x 0 . 6 ) 6 6 top view 0 . 23 +0 . 07 / -0 . 05 09614 march 14, 2014 rev a

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